Session Abstracts
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Lead-free Rework: A Hands-on Overview
Doug Peck, Hands-on Lab
Monday, October 168:00 a.m. - 4:30 p.m.
Recent enactments of RoHS provisions mandate that most electronics products shipped into the EU are lead-free. This full-day, hands-on course will familiarize attendees with global lead-free initiatives and their impact on rework/repair operations. The session will focus on lead-free alloys, component lead and board fi nishes and their impact on rework, new profiling requirements, moisture-sensitive device (MSD) impact, SMT and thru-hole soldering, and visual and X-ray inspection. Discussions also include IPCA-610D and newly published lead-free reference materials. The hands-on portion includes hand installation and removal of lead-free SMT chip capacitors and resistors, SOT and SOIC components, and J-lead PLCCs. This session is limited to 12 attendees.
Lead-free Implementation A-Z: Process, Inspection, and Control
Ron Lasky, Ph.D., PE, Lecture (Day 1)
S. Manian Ramkumar, Hands-on Lab (Day 2)
Tuesday, October 178:00 a.m. - 4:30 p.m.
Wednesday, October 188:00 a.m. - 4:30 p.m.
The RoHS compliance date has come and gone, but there is a strong need for an understanding of, and systematic approach to, meeting these challenging European Directives. This workshop is intended to address this need and help attendees develop RoHS-compliant assembly processes. Its key thrust will be to help companies understand and develop a plan for WEEE/RoHS. The workshop will also present some examples to help take away the "fog" in the lack of clarity of the directives. An overview of similar emerging directives from China, Korea, etc will also be given.
Lead-free Surface Finishes and Compatibility with Soldering
Paul Vianco, Ph.D., Lecture
Tuesday, October 178:00 a.m. - 11:30 p.m.
The implementation of a lead-free solder solution will require a reassessment of the materials set, assembly processes, and reliability expectations of electronic products. This presentation addresses materials issues, reliability topics, and computational models for predicting long-term interconnection performance. Comparisons will be drawn between lead-free and tin/lead solder properties in these areas, using case studies from consumer and highreliability electronics applications.
Failure Analysis Techniques for Process Engineers
Scott Anson, Lecture (a.m.), Hands-on Lab (p.m.)
Tuesday, October 178:00 a.m. - 11:30 p.m.
Tuesday, October 1712:30 p.m. - 4:30 p.m.
Modern SMT components, materials, and processes often have significant opportunity for yield and reliability improvement. The conversion to leadfree solder has only exacerbated these yield and reliability challenges. This seminar will cover fundamental failure analysis techniques, case studies, and cost-effective manufacturing processes. The topics presented will build on existing failure analysis skills and enhance your ability to specify failure analysis services and understand the results.
Lead-free System Compatibility
Ning-Cheng Lee, Ph.D., Lecture
Tuesday, October 1712:30 p.m. - 4:30 p.m.
This course emphasizes the technical knowledge required for implementing lead-free soldering. It covers the background, solders, surface finishes, components, substrates, assembly processes, rework, and reliability of leadfree soldering. Furthermore, it discusses the failure modes, challenges, and solutions for addressing those issues.
Tin Whisker Workshop
Yun Zhang, Ph.D., Lecture
Tuesday, October 1712:30 p.m. - 4:30 p.m.
Tin whiskers, growing spontaneously from tin and tin-alloy coatings, can cause electrical shorts in the circuit and present a long-term reliability problem to the electronic industry. This workshop will provide an overview of the vast literature and latest developments in tin whisker research - from understanding the mechanism to remedies for whisker minimization.
KEYNOTE ADDRESS
Dan Shea, CTO, Celestica
Tuesday, October 176:30 p.m. - 8:00 p.m.
As Celestica's chief technology offi cer, Dan Shea directs the company's technology leadership by ensuring that Celestica anticipates, identifies, and solves the technology challenges facing OEM customers and the broader electronics industry. Dan Shea oversees all technical aspects of Celestica's compliance with emerging environmental legislation.
IPC-7711 Lead-free Certification
Doug Peck, Hands-on Lab
Tuesday, October 178:00 a.m. - 4:30 p.m.
Wednesday, October 188:00 a.m. - 4:30 p.m.
Thursday, October 198:00 a.m. - 4:30 p.m.
The IPC-7711 Certifi ed Specialist (CIS) Lead-free Certifi cation training program is a three-day, hands-on session aimed to familiarize rework/repair personnel with lead-free rework of SMT components using IPC-A-610D as a technical reference. This six-module course addresses the removal/replacement of lead-free components including: SMT chip capacitors and resistors on PCBs; gull-wing SMT devices; and leaded QFP and J-lead devices. Student work will be graded in accordance with IPC Class 3 criteria; and students successfully completing each module will receive an IPC-7711 Certificate. This session is limited to 12 attendees. Prior attendance to Lead-free Rework: A Hands-on Overview, on Monday, October 16 is suggested, but not required.
Applying SPC to Surface Mount Manufacturing
Ronald Lasky, Ph.D., PE, Lecture
Wednesday, October 188:00 a.m. - 4:30 p.m.
Statistical process control (SPC) is the foundation for high yields in SMT processes. In light of this fact, this lecture will cover the basics of how to set up an SPC program for SMT assembly. At the end of the lecture, participants will be able to establish a basic SPC program for their SMT process and use it in a continuous-improvement plan to improve yields and profitability.
Lead-free Reflow and Selective Soldering
Dennis Barbini, Ph.D., Lecture, Hands-on Lab
Wednesday, October 188:00 a.m. - 11:30 p.m.
Thursday, October 198:00 a.m. - 11:30 p.m.
Selective soldering is a process for soldering thru-hole components on the bottom side of an assembly. The implementation of lead-free alloys affects the thermal load of components and board material due to higher process temperatures. Selective soldering has become an interest in the lead-free realm because only areas that come in contact with lead-free solder will reach higher temperatures, while other sections and components remain below critical temperature levels. This session discusses selective soldering parameters, as well as process development and material selection optimization.
Lead-free Wave Soldering Process Troubleshooting
Dennis Barbini, Ph.D., Lecture
Wednesday, October 1812:30 p.m. - 4:30 p.m.
Lead-free wave soldering presents several new challenges from both equipment and process perspectives. Dealing with lead-free alloys requires changes in equipment specifi cations. Understanding the techniques and parameters of the lead-free wave soldering process is key to ensure high yields and a robust process. Types of defects, their causes, and how to avoid them are also discussed, as well as fluxing, preheating, and other process considerations.
Failure and Prevention in Lead-free Assemblies
Viswam Puligandila, Ph.D., Lecture
Thursday, October 198:00 a.m. - 4:30 p.m.
This session will cover the fundamental aspects of lead-free alloy materials, the effects of surface fi nishes, the infl uence of process parameters, and the reliability implications under different loading conditions. A variety of failure mechanisms unique to lead-free interconnections will be discussed.
RoHS 202: Traceability, Certification, and Compliance
Jim Dills, Lecture
Thursday, October 198:00 a.m. - 4:30 p.m.
This presentation describes how and why current RoHS enforcement policies represent significant business risks to manufacturers in the SMT industry. The presentation highlights standardization efforts within the industry, software tools, and how these standards and tools can help manufacturers demonstrate compliance, minimize risk, and ensure traceability of RoHS compliance information.
Surface Mount PCB Design Guidelines for Lead-free Assembly Processes
Vern Solberg, Lecture
Thursday, October 1912:30 a.m. - 4:30 p.m.
This session will enable PCB designers and assembly process specialists an opportunity to achieve success when implementing the more complex fine-pitch quad flat pack ICs, high-density BGA, and fine-pitch chip-scale BGA device families. When adapting these newer, and often higher l/O package families, designers and process engineers must recognize disciplines, capabilities, and limitations within each other's realm.